Our company helps customers successfully implement their chip from requirement specification to delivery of silicon. We offers efficient, reliable and complete design methodology with EDA tools integrated.
The design methodology applies leading edge commercial EDA tools with proprietary tool suites to form a streamlined process for modern ASIC design.
Our state-of-the-art design methodology includes all aspects required for advancing chip design.
State-of-art ASICs engaged in many different scenarios implying lot of dependencies with entire system, so this complexity requires system level design to meet functional, timing and power requirements early as possible. System-level design opportunities includes:
- Architecture development
- Bus planning and configuration
- Virtual prototyping
- Early software development
For each of system-level design areas we provide complex services working tight with customer design teams in way to streamline early development stage and meet project schedule requirements.
Complex architectures of modern ASICs and SoCs as well as high speed and low power are driving factors of RTL design.
Today’s RTL design means not only RTL coding and simple testbench development but requires complex functional verification solutions including verification plan development, code and functional coverage measurements.
To cover this complexity, we developed powerful design and verification environment based on industry-proven methodologies like UVM and leading edge verification solutions from EDA vendors that helps our customer to meet their functional and verification metrics.
Logic synthesis requires a deep knowledge of RTL structure, operating on different functional scenarios, design for test and low power, meet functional equivalence of RTL and netlist.
Our logic design methodology meets all of these requirements in simple but powerful flow that thightly integrates in overall design services offering.
Advanced node technologies lead in a lot different types of faults not only stuck-at and bridge. To handle this complexity modern ASIC and SoC design requires complex test tests covering all of possible manufacturing faults.
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